As semiconductor devices including integrated circuits (IC) operate at higher frequencies, higher data rates and lower voltages, noise in the power and ground (return) lines and supplying sufficient current to accommodate faster circuit switching become increasingly important problems requiring low impedance in the power distribution system. In order to provide low noise, stable power to the IC, impedance in conventional circuits is reduced by use of large numbers of surface mount technology (SMT) capacitors interconnected in parallel placed and as close to the IC as possible.
High power and high frequency ICs are generally mounted on a semiconductor package. The semiconductor package is generally only somewhat larger than the IC or ICs. The semiconductor package, complete with mounted ICs, is conventionally mounted to a larger printed wiring mother board or daughter card.
As frequencies increase and operating voltages continue to drop, increased power must be supplied at faster rates requiring increasingly lower inductance and impedance levels. There is, however, a limitation to the number of SMT chip capacitors that can be mounted in parallel on a semiconductor package because the package is not much larger than the IC itself.
Considerable effort has, therefore, been expended to minimize impedance. One method of minimizing impedance is to embed the capacitor function into the semiconductor package to reduce the distance from the capacitor to the IC. This reduces the inductance and hence the impedance.
U.S. Patent Application Publication No. 2008-0316723A1 to Borland et al., discloses methods of incorporating thin-film capacitors into the build-up layers of a printed wiring board (PWB) such as a semiconductor package, and suggests that a carrier film may be applied to the thin-film capacitor structure to provide additional support during printed wiring board processing. However, Borland et al. does not disclose methods or specific materials that may be utilized.
There is a need for novel methods and materials for carrier layers that provide structural support and improve the process of incorporating a thin-film capacitor into the build-up layers of a semiconductor package.